In electronic digital computers, there are different limitations on the usable memory address space. Even if a microprocessor supports, for example, 32-bit addressing, the integrated circuit package may only allow external access to a lower number of address bits, restricting the memory that can be installed. In modern personal computers, some limits are due to the design of processor, others due to the design of chipsets, BIOS and other hardware and related electrical limitations. Operating system and application software on a hardware platform may not have the capacity to use the full address space physically available.
CPU addressing limits
For performance reasons, all the parallel address lines of an address bus must be valid at the same time, otherwise access to memory would be delayed and performance would be seriously reduced. Integrated circuit packages may have a limit on the number of pins available to provide the memory bus. Different versions of a CPU architecture, in different-sized IC packages, can be designed, trading off reduced package size for reduced pin count and address space. A trade-off might be made between address pins and other functions, restricting the memory physically available to an architecture even if it inherently has a higher capacity. On the other hand, segmented or bank switching designs provide more memory address space than is available in an internal memory address register.
As integrated circuit memory became less costly, it was feasible to design systems with larger and larger physical memory spaces.
Fewer than 16 address pins
Microcontroller devices with integrated I/O and memory on-chip sometimes had no, or a small, address bus available for external devices. For example, a microcontroller family available with a 2 kilobyte address space might have a variant that brought out an 11 line address bus for an external ROM; this could be done by reassigning I/O pins as address bus pins. Some general-purpose processors with integrated ROM split a 16-bit address space between internal ROM and an external 15-bit memory bus.
Some very early computers also had CPUs with fewer than 16 address pins: The MOS Technology 6507 (a reduced pin count version of the 6502) was used in the Atari 2600 and was limited to a 13 line address bus.
16 address bits, 16 address pins
Most 8-bit general-purpose microprocessors have 16-bit address spaces and generate 16 address lines. Examples include the Intel 8080, Intel 8085, Zilog Z80, Motorola 6800, Microchip PIC18, and many others. These processors have 8-bit CPUs with 8-bit data and 16-bit addressing. The memory on these CPUs is addressable at the byte level. This leads to a memory addressable limit of 216 × 1 byte = 65,536 bytes or 64 kilobytes.
16 address bits, 20 address pins: 8086, 8088, 80186 & 80188
The Intel 8086 and derivatives, such as the 8088, 80186 and 80188 form the basis of the popular x86 platform and are the first level of the IA16 architecture. These were 16-bit CPUs with 20-bit addressing. The memory on these CPUs were addressable at the byte level. This led to a memory addressable limit of 220 × 1 byte = 1,048,576 bytes or 1 megabyte.
16 bit addresses, 24 address pins: 80286
The Intel 80286 CPU used a 24-bit addressing scheme. Each memory location was byte-addressable. This results in a total addressable space of 224 × 1 byte = 16,777,216 bytes or 16 megabytes. The 286 and later could also function in real mode, which imposed the addressing limits of the 8086 processor. The 286 had support for virtual memory.
32 bit addresses, 24 address pins
The Intel 80386SX was an economical version of the 386DX. It had a 24-bit addressing scheme, in contrast to 32-bit in the 386DX. Like the 286, the 386SX can address only up to 16 megabytes of memory.
The Motorola 68000 had a 24-bit address space, allowing it to access up to 16 megabytes of memory.
32 bit addresses, 32 address pins
The 386DX had 32-bit addressing, allowing it to address up to 4 gigabytes (4096 megabytes) of memory.
The Motorola 68020, released in 1984, had a 32-bit address space, giving it a maximum addressable memory limit of 4GB. All following chips in the Motorola 68000 series inherited this limit.
32 bit addresses 36 address pins: Pentium Pro (aka P6)
The Pentium Pro and all Pentium 4s have 36-bit addressing, which resulted in total addressable space of 64 gigabytes.
64 bit computing
Modern 64-bit processors such as designs from ARM, Intel or AMD are typically configured with 48 address pins (supporting 256TB of memory) to save on transistor count as more than 256 Terabytes of memory would be impractically expensive. Like previous architectures described here, they are designed to support higher levels of RAM addressing as technology improves.
Operating system RAM limits
CP/M and 8080 addressing limit
The first major operating system for microcomputers was CP/M (Originally standing for Control Program/Monitor, but renamed to the less technical Control Program for Microcomputers, presumably for marketing reasons, despite this causing the forward slash to make relatively little sense). This operating system was compatible with Altair 8800-like Microcomputers, made by Gary Kildall in conjunction with the programming language PL/M, and was licensed to computer manufacturers by Kildall's company Digital Research after it was rejected by Intel. The Intel 8080 used by these computers was an 8-bit processor, with 16-bit address space, which allowed it access up to 64kB of memory; .COM executables used with CP/M have a maximum size of 64kB due to this, as do those used by DOS operating systems for 16-bit microprocessors.
IBM PC and 8086 addressing limit
In the original IBM PC, the basic RAM limit is 640Â kB. This is to allow for hardware addressing space in the upper 384Â kB (upper memory area (UMA)) of the total addressable memory space of 1024Â kB (1Â MB). Ways to overcome the 640k barrier, as it came to be known, involved using special addressing modes available in the 286 and later x86 processors. The 1Â MB total address space was a result of the 20-bit address space limit imposed on the 8086 (and 8088) CPU.
Using the color video buffer space, some third-party utilities could add memory at the top of the 640k conventional memory area, to extend memory up to the base address used by hardware adapters. This could ultimately backfill RAM up to the MDA base address.
Hardware extensions allowed access to more memory than the 8086 CPU could address through paging memory. This memory was known as expanded memory. An industry de facto standard was developed by the LIM consortium, composed of Lotus, Intel and Microsoft. This standard was the Expanded Memory Specification (EMS). Pages of memory from expanded memory hardware were accessible through an addressing window placed into a free area in the UMA space, and by exchanging it for other pages when needed to access other memory. EMS supported 16Â MB of space.
Using a quirk in the 286 CPU architecture, the high memory area (HMA) was accessible, as the first 64Â kB above the 1Â MB limit of 20-bit addressing in the x86 architecture.
Using the 24-bit memory addressing capabilities of the 286 CPU architecture, a total address space of 16Â MB was accessible. Memory above the 1Â MB limit was called extended memory. However the area between 640Â kB and 1Â MB was reserved for hardware addressing in IBM PC compatibles. DOS and other real mode programs, limited to 20-bit addresses, could only access this space through EMS emulation on the extended memory, or an EMS analog for extended memory. Microsoft developed a standard known as the Extended Memory Specification (XMS). Accessing the memory above the HMA required usage of the protected mode of the 286 CPU.
With the development of the i386 CPU architecture, the address space was moved to 32-bit addressing, and a limit of 4Â GB. With this CPU, access to 16Â MB memory areas was available to DOS programs that used DOS extenders, such as DOS/4GW, MiniGW/16, MiniGW, and others. Initially a de facto industry memory standard for interaction known as VCPI was developed. Later, a Microsoft standard supplanted this, known as the DPMI. These standards allowed direct access to the 16Â MB space, instead of the paging scheme used by EMS and XMS.
16-bit OS/2 RAM limit
16-bit OS/2 was limited to 15Â MB, due to reserve space designed into the operating system. It reserved the top 1Â MB of the 16Â MB 24-bit address space for non-memory (from 15Â MB to 16Â MB).
32-bit x86 RAM limit
In non-PAE modes of x86 processors, the RAM is always limited to 3.76GB
Limits on memory and address space vary by platform and operating system, and on Windows by whether the IMAGE_FILE_LARGE_ADDRESS_AWARE value of the LOADED_IMAGE structure and 4-gigabyte tuning (4GT) are in use.
Limits on physical memory for 32-bit platforms also depend on the Physical Address Extension (PAE), which allows 32-bit systems to use more than 4Â GB of physical memory.
PAE and 64-bit systems can address up to the full address space of the x86 processor.
See also
- DOS memory management
External links
- MSDN Article: Memory Limits for Windows Releases
- Microsoft Help & Support: Explaining The Issue.
- Windows Vista SP1 Details About The RAM Limit
